===DRAFT============ RELEASE NOTES ============= Product : GNU C/C++ Compiler Toolkit for ARC Processors MileStone : Support and upgrade release of the ARC GNU Tools Version : GNU binutils 2.15 codito-20060612-release GCC 3.4.6 codito 20060612 [ derived from FSF release on 6th March 2006] Date : June 12, 2006 Table of Contents ----------------- 1. Overview 2. Features Supported 3. Major changes in this release 4. Known Limitations and Defects 5. Contact Information 6. Reference 1. Overview ------------ This is a support release for the GCC-3.4.x based GNU toolchain for the ARC cores. The compiler has been upgraded to the final release on the 3.4.x branch by FSF. Also included are some improvement/bug fixes and an ABI change (Ref. section 3 below). 2. Features Supported ---------------------- 2.1 Features of support release #2 (June 12 2006) ----------------------------------------------------------- * Fix for missing headers in crosstool based uClibc builds. * GCC upgraded to version 3.4.6, based on sources released by FSF on 6th March 2006. * Peephole optimization improvements. * Value of R_ARC_GOT32 changed from 0x33 to 0x3B * New relocation R_ARC_GOTPC32 with value 0x33 added. * Keywords 'can_shortcut' and 'cannot_shortcut' for extension directives made case-independent. * Miscellaneous bug-fixes. 2.2 Features of optimizations release #1 (February 22 2006) ----------------------------------------------------------- * A crosstool based build mechanism for arc-linux-uclibc target. * DFA description of ARC700 pipeline behaviour for improved scheduling of instructions, in the compiler. * C++ language support in the compiler. * Support for Aurora SIMD extension instructions in binutils. * Support for -mlong-calls switch. * Support for 'long_call' and 'short_call' function attributes. * Char variables now default to 'unsigned char' as against 'signed char' earlier. * Dummy -msoft-float flag support in the compiler. * Support for sibling call optimizations. * Support for conditional branch pseudo-mnemonics BRGT , BRLE, BRHI, BRLS, BRCS. * Improved error reporting by the linker (in case of relocation overflows). * Improved 16-bit code generation in function pro/epilogues. * Fixes to eliminate redundant code generation (unnecessary moves eliminated). * Filling up the gaps in text section due to alignment, with nops instead of 0x00. * GCC upgraded to version 3.4.5 * Miscellaneous other bug fixes. 2.3 Features of support release #1 (July 25 2005) ------------------------------------------------- * Handling of extension instructions in the binutils rewritten. * New flags added to the compiler and binutils (See section 3 below). * Bug #1366 in the generation of min instructions fixed. * Bug #1307 in the generation of multiple shifts for ARCtangent-A4 fixed. * Bug #1378 in the costs of multiply instructions fixed. * Bug #1310 with generation of bbit instructions fixed. * Bug #1301 with spurious add2 generation in A4 code fixed. * Bugs #1284, #1294 fixed, allowing brk generation with builtins for all cores. * Bug #1011 with bic instruction generation fixed. * Bug #1293 fixed, disallowing generation of divaw instruction generation and support for the same in binutils, for ARC700 base case. * Bug #1309 with the support for lsl instructions in the assembler fixed. * Miscellaneous code clean-ups. 2.4 Features of the first upgrade release (May 23 2005) ------------------------------------------------------- * Improved ABI compatibility * Support for extension instructions for ARCtangent-A5, ARC600 and ARC700 processors * Support for builtins (compiler intrinsics) as an interface for generating assembly instructions. * Better support for DWARF-2 debug information generation. * newlib is now built for big-endian targets as well. * Numerous bug-fixes and cleanups. 3. Major back-end changes in this release ----------------------------------------- * The ABI for ARC has been changed to reassign the value 0x33 to a new relocation type R_ARC_GOTPC32. This value was earlier used for the relocation R_ARC_GOT32, which has now been assign a value of 0x3B. However, the functionality of R_ARC_GOT32 has also been modified and R_ARC_GOTPC32 is now functionally equivalent to the older semantics of R_ARC_GOT32 (GOT+G+A-P) [Ref. Sys V psABI extension for the ARC Cores]. The new interpretation of R_ARC_GOT32 is G+A, although this relocation is not presently generated by the GNU Toolchain. Thus, the change retains binary compatibility between the old and new versions (since the meaning of 0x33 is unchanged), but any programs using the values of the relocations explicitly will have to be recompiled after this change. For the list of changes in the earlier releases, please see the corresponding release notes. 4. Known Limitations and Defects -------------------------------- * The ARC linker has a bug in handling ARCtangent-A4 jumps to upper half of the 26-bit instruction range, which can cause a link-time crash. For a beta-fix, please contact arc-support@codito.com * Position Independent Code generation support is only available for the ARC700 processor. * The description for the DFA based pipeline hazard recognizer and instruction scheduler is present only for ARC700, so the compiler still uses the old instruction scheduler for older architecture variants. * Some applications are known to fail, if the -lpthread flag is passed at link-time in the build. 5. Contact Information ---------------------- In case of any defects please contact arc-support@codito.com. If you have a support contract, please use the support site at http://support.codito.com. 6. References ------------- * ARC700 ISA Reference Manual * ARC GNU Tools User Guide * Sys V ABI Extension for ELF for the ARC * Aurora SIMD extensions to the ARC700 ISA. * The finite state automaton based pipeline hazard recognizer and instruction scheduler in GCC - by Vladimir N. Makarov (GCC Summit 2003 proceedings) [Link: http://www.gccsummit.org/2003 ] Tools Team Codito Technologies